Reliability (semiconductor)

Reliability of semiconductor devices can be summarized as follows:

  1. Semiconductor devices are very sensitive to impurities and particles. Therefore, to manufacture these devices it is necessary to manage many processes while accurately controlling the level of impurities and particles. The finished product quality depends upon the many layered relationship of each interacting substance in the semiconductor, including metallization, chip material (list of semiconductor materials) and package.
  2. The problems of micro-processes, and thin films and must be fully understood as they apply to metallization and bonding wire bonding. It is also necessary to analyze surface phenomena from the aspect of thin films.
  3. Due to the rapid advances in technology, many new devices are developed using new materials and processes, and design calendar time is limited due to non-recurring engineering constraints, plus time to market concerns. Consequently, it is not possible to base new designs on the reliability of existing devices.
  4. To achieve economy of scale, semiconductor products are manufactured in high volume. Furthermore repair of finished semiconductor products is impractical. Therefore incorporation of reliability at the design stage and reduction of variation in the production stage have become essential.
  5. Reliability of semiconductor devices may depend on assembly, use, and environmental conditions. Stress factors effecting device reliability include gas, dust, contamination, voltage, current density, temperature, humidity, mechanical stress, vibration, shock, radiation, pressure, and intensity of magnetic and electrical fields.

Design factors affecting semiconductor reliability include: voltage derating, power derating, current derating, metastability, logic timing margins (logic simulation), timing analysis, temperature derating, and process control.

Contents

Methods of improvement

Reliability of semiconductors is kept high through several methods. Cleanrooms control impurities, process control controls processing, and burn-in (short term operation at extremes) and probe and test reduce escapes. Probe (wafer prober) tests the semiconductor die, prior to packaging, via micro-probes connected to test equipment. Wafer testing tests the packaged device, often pre-, and post burn-in for a set of parameters that assure operation. Process and design weaknesses are identified by applying a set of stress tests in the qualification phase of the semiconductors before their market introduction e. g. according to the AEC Q100 and Q101 stress qualifications.[1]

Failure mechanisms

Failure mechanisms of electronic semiconductor devices fall in the following categories

  1. Material-interaction-induced mechanisms.
  2. Stress-induced mechanisms.
  3. Mechanically induced failure mechanisms.
  4. Environmentally induced failure mechanisms.

Material-interaction-induced mechanisms

  1. Field-effect transistor gate-metal sinking
  2. Ohmic contact degradation
  3. Channel degradation
  4. Surface-state effects
  5. Package molding contamination—impurities in packaging compounds cause electrical failure

Stress-induced failure mechanisms

  1. Electromigration – electrically induced movement of the materials in the chip
  2. Burnout – localized overstress
  3. Hot Electron Trapping – due to overdrive in power RF circuits
  4. Electrical Stress – Electrostatic discharge, High Electro-Magnetic Fields (HIRF), Latch-up overvoltage, overcurrent

Mechanically induced failure mechanisms

  1. Die fracture – due to mis-match of thermal expansion coefficients
  2. Die-attach voids – manufacturing defect—screenable with Scanning Acoustic Microscopy.
  3. Solder joint failure by creep fatigue or intermetallics cracks.

Environmentally induced failure mechanisms

  1. Humidity effects – moisture absorption by the package and circuit
  2. Hydrogen effects – Hydrogen induced breakdown of portions of the circuit (Metal)

See also

References

  1. ^ AEC Documents

Bibliography